Name : Joungho Kim
E-mail : firstname.lastname@example.org
Tel : +82-42-350-3458
Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design. In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently Electrical Engineering Department Chair at KAIST. Also, he is director of 3DIC-RC (3DIC Research Center) supported by Hyniz Inc., and SAE-RC (Smart Automotive Electronics Research Center) supported by KET Inc.
Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, System-in-Package(SiP), multi-layer PCB, and wireless power transfer technology. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission of 3D IC and SiP. He has successfully demonstrated low noise and high performance designs of numerous SiP’s for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during an academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale CA. He was responsible for low noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices. Recently, he started a new research on wireless power transfer technology using magnetic field resonance. He has been one of the co-leaders in a national project, OLEV (Online Electrical Vehicle), for EMI and EMF reduction design. The OLEV was selected as one of the 50 Best Inventions in 2010 by Times Magazine.
He has authored and co-authored over 370 technical papers published at refereed journals and conference proceedings in modeling, design, and measurement of 3D IC, SiP, PCB, and wireless power transfer. Also, he has given more than 174 invited talks and tutorials at the academia and the related industries. He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, Best Faculty Research Award of KAIST in 2008, National 100 Best Project Award in 2009, and KAIST International Collaboration Award in 2010, respectively. Dr. Joungho Kim was the symposium chair of IEEE EDAPS 2008 Symposium, and is the TPC chair of APEMC 2011. He is appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. He received Technology Achievement Award from IEEE Electromagnetic Society in 2010. Currently, he is TPC member of EPEPS (Electrical Performance of Electronic Packaging and System). He is also an associated editor of the IEEE Transactions of Electromagnetic Compatibility. He served as a guest editor of the special issue in the IEEE Transactions of Electromagnetic Compatibility for PCB level signal integrity, power integrity, and EMI/EMC in 2010, and also as a guest editor of the special issue in the IEEE Transactions of Advanced Packaging for TSV (Through-Silicon-Via) in 2011.
Department of Electrical Engineering and Computer Science
KAIST(Korea Advanced Institute of Science and Technology)
373-1 Kusong-dong, Yusung-gu, Taejon 305-701, Korea
Tel) +82-42-350-3458 Fax)+82-42-350-8058
Hyundai APT 103-806
Taejon, Korea, 305-340
Chip-Package Co-design, SiP(System-in-Package) Design,
TSV-Based 3D IC Design
Signal Integrity, Power Integrity, EMI/EMC
Ph.D., Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan, September, 1993.
Thesis title: Ultrafast Optical Techniques for High-speed Devices and MM-Wave Circuit Testing.
Adviser : Prof. Gerard Mourou
Master of Science, Electrical Engineering, Seoul National University, Seoul, Korea, February, 10, 1986.
Bachelor of Science, Electrical Engineering, Seoul National University, Seoul, Korea, February, 10, 1984.
Professor, Department of Electrical Engineering and Computer Science, KAIST(Korea Advanced Institute of Science and Technology), March, 2005 to present.
◆ Chip-Package Co-design and simulation
◆ SiP (System-In-Package) Modeling, Design, and Measurement
◆ 3D Package: Design, Measurement and Modeling.
◆ TSV-Based 3D IC Design
◆Signal Integrity, Power Integrity
◆ Interconnection Design and Modeling for >10 GHz Serial Differential Interconnection Systems.
◆ High-speed and Performance Package Design and Modeling
◆ PCB level signal integrity, SSN(simultaneous switching noise), Ground Bounce, and EMI/EMC
Associate Professor, Department of Electrical Engineering and Computer Science, KAIST(Korea Advanced Institute of Science and Technology), March, 1999 to 2005.
Assistant Professor, Department of Electrical Engineering and Computer Science, KAIST(Korea Advanced Institute of Science and Technology), March, 1996 to February, 1999.
Technical Consultant, Hyundai Motor Company, EMI/EMC, from Aug. 2004 to 2005.
Technical Consultant, SilImage Inc. Signal Integrity and Package Design engineer, from Aug. 2002 to present.
◆ HDMI Package Design
◆ HDMI Interconnect Modeling and Design (PCB, Connector, and Cable)
◆ SATA Package Design
◆ SATA Interconnect Modeling and Design (PCB and Cable)
◆ FC Package Design
◆ FC Interconnect Modeling and Design.(PCB and Cable)
Staff Engineer, SilImage Inc. Signal Integrity and Package Design engineer, from July 2001 to Aug. 2002.
◆ SATA Package Design
◆ SATA Product: [Sil3124:Sable(HSBGA)], [Polaris], [Sil3114: Taurus(176pin TQFP)], [Sil3112:Athena (144 pin TQFP)], [Sil3512: Athena_LPC (128pin TQFP)], [Sil3611:Calypso (80 pin TQFP, 100 pin TQFP, 80 pin MQFP)],
[Sil3612:Tango (15mmx15mm LBGA)], [Sil3012:Gemini (80 pin TQFP)], [Hydra (27mmx27mm HSBGA)], [Saturn].
◆ FC Package Design.
◆ FC Product: [Sil2020: Rainer (64 pin TQFP)], [Sil2022:JQueen( 64 pin TQFP, 64 pin MQFP)], [Sil2024,Quadra ( 23mmx23mm MCM-PBGA)], [Mercury 2X].
◆ Panel Link Product: Sil9993 Receiver( 100pin TQFP), Sil9190. Riker(80pin TQFP), Troi(144pin E-pad TQFP)
Principle Research Engineer, Samsung Electronics Inc. in Korea, September, 1994 to January, 1996.
◆ 1 Gbit DRAM Design
◆ 16 Mbit DRAM Design
Research Engineer, Picometrix Inc. in U.S, September, 1993 to July, 1994.
◆ Design of 70 GHz PX-D7 Photo-receiver Module
◆ Design and fabrication of MSM LT-GaAs photo-detector.
◆ Ultrafast Picosecond Sampling System.
Research Assistant, University of Michigan, January, 1990, to July, 1993.
◆ IEEE Transactions on Electromagnetic Compatibility, Special Issue Paper Editor: 2009. PCB Level Signal Integrity, Power Integrity, and EMI/EMC.
◆ EMC Kyoto, Special session chair, IC Level EMI/EMC
◆ IEEE EDAPS (Electrical Design of Advanced Package and Systems), General Chair, Seoul, 2008
◆ VLSI Package Workshop, International Program Committee, Kyoto, 2008.
◆ Chapter Chair of Daejon Chapter, IEEE CPMT Society, 2007-
◆ IEEE EDAPS (Electrical Design of Advanced Package and Systems) 2007, International Steering Committee, Taiwan
◆ AP-EMC, Special Session Chair, Singapore, 2007.
◆ IEEE EMC Symposium, International Committee Member, Hawai, 2007.
◆ IEEE EMC Symposium, Special Session Chair, Hawai, 2007.
◆ IEEE ASSCC Panel Session Chair: SoC or SiP, Jeju Island, 2007.
◆ VLSI Package Workshop, International Program Committee, Kyoto, 2006.
◆ IEEE EPTC, Technical Program Committee Member, Singapore, 2005-
◆ Associated Editor of IEEE Transactions on Electromagnetic Compatibility. 2004~
◆ EDAPS (Electrical Design of Advanced Package and Systems) 2003~, Chair and Co-Chair, Seoul
◆ Committee Chair in Package Group in Korea Microwave Engineering Society, since 1998-.
◆ International Advisory Committee Member, 7th IEEE International Conference on Terahertz Electronics.
◆ InterPack2001 Conference, Committee Member, 2001.
◆ IEEE CPMT Society TC-12 technical program committee member, since 1998-
◆ IEEE member, 1996- present.
◆ IEEE student member, 1990
Korea Government Merit Scholarship for Studying Abroad, 1989.
◆ KAIST Academic Achievement Award, 2006.2
◆ KAIST Best Research Faculty Award, 2007. 2
(1) System-In-Package Modeling and Design.
Signal integrity analysis of high-performance chip and package.
Power integrity analysis of high-performance chip and package.
EMI analysis of high-performance chip and packages.
Multi-layer interconnection modeling and design
Pre-emphasis and Equalizer Design
High-speed Channel Modeling and Measurement
RF-ID SiP Design
UWB SiP Design
(2) RFID Reader SiP/SoC Design
Reader SoC Design
Reader SiP Design
13.56MHz, UHF, 433MHz RFID Reader Design
Antenna Design for RFID Reader
(3) Chip, SiP, System level signal integrity, power integrity, and EMI analysis and design.
Signal integrity analysis
Power integrity analysis
Inter-symbol interference analysis
LNA Noise Issues
Mixer Noise Issues
ADC/DAC Noise Issues
DDR Module design
Backplane PCB design.
Via modeling and effect on signal integrity
Edge radiation from Power/ground resonance
Power/ground noise isolation on PCB
Power/Ground Noise filter design.
Optimal decoupling capacitor design.
Ground filling and guard effect
Mender line modeling and design..
Ground guard fence
(4) Embedded Passives on Chip, Package and PCB
Modeling and design of embedded capacitors on multi-layer PCB
Modeling and design of embedded capacitors on BGA type packages.
Modeling and design of Embedded termination resistor
Modeling and design of Embedded filter
Modeling and design of Embedded inductor
(5) SerDes Channel Modeling and Design for GHz Serial Differential Interconnection Systems
HDMI/UDI PCB and Backplane Modeling and Design
HDMI/UDI Package Modeling and Design
SATA PCB and Backplane Modeling and Design
SATA Package Modeling and Design
FC PCB and Backplane Modeling and Design.
FC Package Modeling and Design.
Signal integrity analysis of GHz serial channel.
Cable and Connector Modeling and Design
(6) Test, Modeling and Design of Connector and Sockets.
Test, modeling and design of high-speed connectors.
Cat 5E Modular jack design
Radiated emission from FPC( Flexible Printed Circuit)
Jitter and Timing Analysis